The convention for register usage and C linkage commonly used on desktop PowerPC machines. Similar, but not identical to the EABI.
An on-chip debugging interface, largely eliminating the need for expensive In-Circuit Emulators.
The magic communications co-processor in Motorola PowerQUICC devices. It contains SCCs and SMCs, and performs SDMA and IDMA.
Depending on the context, this may refer to the PowerPC core itself, or the physical processor device (including CPM, SIU, packaging etc) as a single unit.
A form a data transfer directly between memory and a peripheral or between memory and memory, without normal program intervention.
The convention for register usage and C linkage commonly used on embedded PowerPC machines, derived from the ABI.
The 100 Mbps (100Base) Ethernet controller, present on 'T' devices such as the 860T and 855T.
http://www.gnu.org/copyleft/gpl.html
The licenses under which the Linux kernel and much of the utility and library code necessary to build a complete system may be copied, distributed and modified. Each portion of the software is copyright by its respected copyright holder, and you must comply with the terms of the license in order to legally copy (and hence use) it. One significant requirement is that you freely redistribute any modifications you make; if you can't cope with this, embedded Linux isn't for you.
A general purpose DMA engine with relatively limited throughput provided by the microcoded CPM, for use with external peripherals or memory-to-memory transfers.
The IEEE Ethernet standard control interface used to communicate between the on-chip Ethernet controller and the external PHY.
CPU component which maps kernel- and user-space virtual addresses to physical addresses, and is an integral part of Linux kernel operation.
The IEEE Ethernet standard interface between the external physical layer transceiver and the on-chip ethernet controller in a PowerQUICC device. Often used to refer to the external transceiver itself, the PHY is controlled more or less transparently to software via the MII.
The high performance module(s) within the CPM which implement the lowest layer of various serial protocols, such as Asynchronous serial (UART), 10 Mbps Ethernet, HDLC etc.
Provides much of the external interfacing logic. It's the other major module on Motorola PowerQUICC devices alongside the CPU core and CPM.
A relatively simple synchronous serial interface for connecting low speed external devices using minimal wires.
A lower performance version of the SCCs with more limited functionality, particularly useful for serial debug ports and low throughput serial protocols.
Generically, this refers to any device capable of implementing a variety of asynchronous serial protocols, such as RS-232, HDLC and SDLC. In this context, it refers to the operating mode of the SCCs which provides this functionality.
A highly flexible bus interfacing machine unit allowing external peripherals with an extremely wide variety of interfacing requirements to be connected directly to the CPU.